Integrated circuits generally rely on precise clock signals to perform their intended functions. Integrated circuit performance may suffer if the clock signal is degraded, such as from duty cycle distortion of the clock signal. Duty cycle refers to the relative relation between the positive and negative pulse widths of the clock signal (e.g., a sinusoidal signal). Duty cycle distortion may occur due, for example, to process, voltage, and temperature (PVT) variations.
As integrated circuit performance and interface speeds increase, there is a greater need to control duty cycle distortion because the distortion, for example, may degrade a larger percentage of the shrinking clock period. Furthermore, system and interface requirements increasingly utilize both edges (i.e., the rising and falling edges or different phases of the clock signal) to increase performance and thus, duty cycle distortion becomes increasingly significant.
Additionally, timing margins may be reduced when the duty cycle of the incoming clock is not matched or when internal circuits contribute to the distortion of the duty cycle. Consequently, duty cycle distortion may make it difficult to meet system timing requirements and may affect timing equations. As a result, there is a need for techniques to reduce duty cycle distortion.